Spent last
week at the brilliant IPFA (23rd International Symposium on the Physical and
Failure Analysis of Integrated Circuits to give it its full title) at
the magnificent Marina Bay Sands in Singapore. See http://ieee-ipfa.org/ for the program. Last time I went was in 2014
and a lot has happened since. In even years IPFA is held in Singapore and in
odd years another location in Asia, so it is a truly international conference
which brings together the Microelectronics FA community from all parts of the
world. This year was the best ever with more participants and more exhibitors
than ever before. Monday, the first day, was dedicated to tutorials from some
of the “gurus” of reliability and FA such as Christian Boit (Berlin), Tan Cher
Ming, Taiwan, Chris Henderson (USA) Pey Kin Leong and Arief Budiman, both from SUTD Singapore. On
a personal note, Pey Kin Leong introduced me to Atomic Force Microscopy when we
worked together at Institute of Microelectronics twenty years ago and he was one of the
driving forces behind IPFA in the early years.
For me,
one of the most fascinating aspects was Christian Boit showing how backside
optical techniques can be extended down to nanometre scale using a combination
of advanced immersion lenses, shorter wavelengths and aggressive thinning of
the silicon. Possible but technically very challenging.
Tuesday kicked off with
the keynote presentation “More than 2D: The Industry Wide Challenge“ by J. Xie of Altera. When people talk about “more than 2D” we
often think it terms of through silicon vias (TSVs) and silicon interposers but
Xie believes there is a long way to go using less costly alternatives. In
particular Altera is working on a “silicon bridge technology” to bring chips
closer together. The picture below,
taken from the Altera paper “Enabling Next-Generation Platforms Using Altera’s
3D System-in-Package Technology” and shows the concept and highlights the
advantages compared with Si interposers. Think the big challenge will be the
dimensional stability of the laminate substrate which has a big TCE mismatch
with the Si chips.
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| Altera’s Silicon Bridge Technology |
I shouldn’t leave the Xie’s keynote address without
mentioning his analogy of the advances in microelectronics being akin to “Shrinking
Manhattan to the size of a credit card”.
Among other papers that appealed to me was “Localization
Techniques for Finding Embedded Defects in Stacked Die Package” by Lai-Seng
Yeoh, Kok-Cheng Chong and Susan Li at Cypress Semiconductor. They used lock-in
infrared thermography to isolate the fault to a specific die in the stack and
then some very patient de-processing to identify the root cause of failure.
And, of course there was the exhibition to visit. More than
thirty five exhibitions stands and again a chance to meet up with people I
haven’t seen for a while. A special mention must go to FEI and Digit Concept, the IPFA Platinum and Gold sponsors
who have been supporting IPFA consistently over many years. FEI makes electron
microscopes and Focused Ion Beam Systems (FIBs) and is almost certainly the
biggest company in the field. https://www.fei.com/
Found out that if you Google “FEI” for images you get a very
pretty Korean singer who doesn’t look anything like an SEM or FIB.
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| Fei |
Should mention one of FEI’s competitors, JEOL, at the
exhibition whose Auger system I used on and off for over 18 years. When I spoke
to my ex colleague at IME, I was amazed to learn that the old Auger system is
still running after more than 20 years. When it was first installed we had a
lot of teething problems but after that it proved pretty reliable.
The IPFA Gold Sponsor, Digit
Concept, specialises in laser decapsulation equipment. With the
increased use of copper wire and more chip stacking, decapsulation continues to
get more challenging. Another company in the decapsulation business and at the
exhibition was JIACO Instruments which offers a unique atmospheric plasma system.
It’s a fairly new start-up company spun out from the University of Delft in
Holland. The CEO, Jiaqi Tang, is very hands-on and did some excellent work
about three years ago to remove stubborn mold compound from copper wire bonded
test chips when I was working at IME.
I was fortunate enough to be invited to the VIP dinner at
Alkaff mansion where we enjoyed a delicious dinner accompanied by plenty of
wine in a delightful setting. A great chance to re-connect with friends and
colleagues.
Alkaff Mansion
IPFA General Chair Vinod Narang opening the Champagne
Wednesday was another
full day with a poster session as well as two parallel sessions of oral
presentations and the exhibition to visit. For me, one of the highlights was “Challenges
and Improvement of Reliability in Advanced Wafer Level Packaging” by another ex
IME colleague S. W. Yoon now at STATS ChipPAC. Everyone likes the idea of a
chip scale package which is no bigger than the chip but thinned down silicon
chips are delicate little things and easily damaged by handling. Yoon described one option for protecting them
with a thin polymer overcoat. This is “an Encapsulated Wafer Level Chip Scale
Package, eWLSCP for short. Another advantage is that the encapsulated chips are
robust enough to put into a socket for testing, but you probably wouldn’t want
to try it many times. Although everyone
wants the package to be no bigger than the chip, in practice there may
be too many I/Os to fit in the chip area,
in which case a fan-out solution is needed, Fan-Out Wafer Level Packaging
(FOWLP). Yoon went out to discuss the
reliability challenges associated with Through Silicon Vias (TSVs) and the problems
of getting the heat out from stacked chips.
An interesting approach
to top-down delayering techniques was described by T. Hrncir in which an FIB
beam is directed towards the chip surface at a glancing angle while rocking the
sample back and forth to minimise “curtaining”. The results looked impressive
but the technique requires the device to be cleaved at the area of interest.
Which explains why one of the co-authors, Efrat Moyal was from Lattice Gear,
one of the exhibitors, which makes cleaving equipment to do the job.
One of my ex-colleagues
R Gopalkrishnan presented a paper on “Failure Mechanisms in Encapsulated Copper
Wire-Bonded Devices”. Of particular interest to me was his
description of a low
tech, low cost method of decapsulation of copper wire bonded ICs. It looks
almost too good to be true, a beaker, some acid and a power supply are all you
need.
Simple Decapsulation Technique
Did I forget to mention
the food? IPFA, like all other Singapore conferences I have been to, provides
generous amounts of delicious food at morning coffee break, lunch and afternoon
tea break. But I tried not to go overboard because in the evening we had a
Chinese banquet at the Majestic Restaurant in the Gardens by the Bay, a short
walk from the conference. The banquet
was kicked off with a traditional Lion Dance. Can’t remember how many courses
there were but sure nobody left hungry.
Lion Dance to kick off the Banquet
Thursday was the final day and after the first
two papers, an invited paper by Christian Boit on “From IC Debug to Hardware
Security Risk: The Power of Backside Access and Optical Interaction followed
by Differential C-AFM System
for Semiconductor Failure Analysis, both of which were fascinating in different ways, I headed out
to Science Park 2 to visit Wintech Nano Technology, one of the key FA service
providers in Singapore where Zhang Zhe gave me a tour round the facility which I thought was impressive. If you want
to see what facilities they have I suggest you visit their website
The Managing Director,
Li Xiaomin, founded the company just over ten years ago and has done a
fantastic job of building it up. He is another ex IME person and the FA
capabilities in Wintech are now far beyond the capabilities in IME. They have
already set up a facility in Suzhou, China. Almost all the exhibitors I spoke
to were telling me that the big growth opportunities are in China, and at the
same time were telling me how difficult it is to break into the market.
Back at the
conference and after my final lunch I was particularly interested in the paper
by C K Lee of NUS on Reliability and Failure Analysis of MEMS/NEMS Switches
since I plan to be doing a course on MEMS Packaging and Reliability next month.
Much of the work focused on mechanical robustness but it was interesting that
the packaging technology has an impact because of oxidation of molybdenum used
as an electrical switch.
Another paper that
hit all the right buttons was “Decapsulation of Copper Wire Devices with High
Tg Mold Compound using Microwave Induced Plasma by Jiaqi Tang who I
mentioned earlier. So the technical sessions ended on a high note before the
closing ceremony. Next year IPFA will be in Chengdu, China. Should be
interesting.
Relaxed in the evening
having dinner with my friend My at Wine Connection in Cuppage Terrace before
saying goodbye to her as she was returning to Vietnam the next day.
After IPFA
Took the train across
the causeway to Johor Bahru (JB) on Saturday where I am busy preparing my notes
for the courses on Microelectronics Principles of Reliability Testing ForSemiconductor & Microelectronics Industry this coming Thursday and Friday
in Singapore and the following Monday and Tuesday in Manila. Also the notes for Packaging Technology & Reliability Issues For Micro- ElectromechanicalSystems scheduled for 8 & 9 August in Penang and 11 & 12 August 2016 in
Manila.
It’s the first time I have been in JB here since
departing for my "train home" almost two years ago and a few things
have changed. On the plus side you can easily buy tickets online, but against
that it now takes three trains to get from Woodlands to KL. Far less convenient
than 20 years ago when through trains departed from Tanjong Pagar in the city.
Singapore and Malaysia have just signed an MOU for a high speed KL to Singapore
rail link but I'll believe it when I see it.
Old and new in JB
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| The Red House in JB |
